The present invention relates to digital filtering of electronic signals, and more particularly to a Finite Impulse Response (FIR) filter based upon squaring.
The standard FIR filter convolution satisfies the following equation: EQU z(t)=SUM{y(t-i)*C(T-1-i),(i,0,T-1)}
where z(t) is the filtered output at time t, C is a filter coefficient for each of T stages, y(t) is the input at time t, and SUM is the sum of the products of y(t) and C for the range of i between 0 and T-1. In such a FIR filter configuration the complexity in gate count, G(M,N), is proportional to the number of cross-terms between multiplicands, and is approximately given by: EQU G(M,N)=11M*N-10N-5M (N&gt;=1, M&gt;=2)
for an M+N bit result of a multiply. The number of gates determines the amount of silicon area required in an integrated circuit in order to implement the FIR filter.
What is desired is a simpler configuration for a FIR filter that reduces the complexity, and thus the number of gates, in order to minimize the amount of silicon in an integrated circuit necessary to implement the filter.